This invention relates to an electrically erasable and programmable read only memory (abbreviated as "EEPROM"), and more particularly to the EEPROM designed to perform writing and erasure at different sections.
FIG. 1 shows the arrangement of the conventional EEPROM cell. Reference numeral 1 represents a p type single crystal silicon substrate. A field oxide film 2 is selectively formed on the surface of the substrate 1. The island regions of the substrate 1 are separated from each other by the field oxide film 2. Electrically isolated n.sup.+ type source region 3 and drain region 4 are formed on these island regions. A gate oxide film 5 is formed on that portion of the substrate 1 which includes a channel region lying between the source and drain regions 3, 4. A floating gate 6 is set on the gate oxide film 5. An insulation film 7 is formed on the floating gate 6. A control gate 8 is laid on the insulation film 7. A portion of the control gate 8 lies over the field oxide film 2. An insulating film 9 covers the surface of the structure including the control gate 8. A source electrode 10 and drain electrode 11 formed on the insulation film 9. The electrodes 10 and 11 extend through contact holes (refer to Section A of FIG. 1) and contact the source and drain regions. An n.sup.+ type diffusion region 4', an extension of the drain region 4, is provided on the surface of the substrate 1 adjacent to the island. A thin insulation film 12 is formed on the diffusion region 4'. An extension 6' of the floating gate 6 is provided on the thin insulation film 12. The n.sup.+ type diffusion region 4', thin insulation film 12 and the extension 6' of the floating gate 6 jointly constitute an MOS capacitor B (FIG. 1).
When, with the EEPROM cell described above, a high voltage, for example 20 volts, is applied between the drain electrode 11 and control gate 8, tunnel current flows between the extension 6' of the floating gate 6 and n.sup.+ type diffusion region 4' through the thin insulation film 12, whereby the floating gate 6 is charged or discharged. The EEPROM cell stores data "0" when the floating gate 6 is charged. It stores data "1" when the floating gate 6 is not charged. The threshold voltage V.sub.TH of the transistor A (FIG. 1) represents high when the floating gate 6 is charged, and low when the gate 6 is not charged.
However, with the floating gate 6 repeatedly charged and discharged to alter the stored information, using a constant voltage impressed between the drain electrode 11 and control gate 8, the resultant threshold voltage of the transistor A (FIG. 1) will vary little by little. More specifically, as shown in FIG. 2, with the floating gate repeatedly charged and discharged, the width of threshold voltage change of the transistor A is somewhat enlarged in early several cycles and then it is relatively constant for a while, and it begins to reduce, finally failing to distinguish data "0" from data "1". This event is explained by the following reasons.
When the floating gate 6 is charged or discharged as the tunnel current flows through the thin insulation film 12, an intense electric field of 8 to 10 MV/cm is applied on the film 12, and positive electric charge is trapped in the film 12. Since not so many such trapsites exist within the film 12, they are soon saturated. The positive charge undergoes substantially no change. The tunnel current inevitably flows with greater ease by positive charge trapped in the thin insulation film 12, leading to noticeable changes in the threshold voltage.
While the tunnel current is flowing through the thin insulation film 12, electrons are also trapped in the thin insulation film 12. They are not so rapidly trapped as positive charge, but they are trapped steadily and exceed the quantities of positive charge stored in the thin insulation film 12 sometime later. As a result, the tunnel current flows with greater difficulty, thereby reducing the rate of variations in the threshold voltage. The intense electric field applied on the film 12 increases the electron-trapping sites in the film 12. Consequently, negative charge stored in the thin insulation film 12 is not saturated. The threshold voltage changes at a steadily decreasing rate. In some cases, dielectric breakdown occurs caused by the internal electric field generated by the electric charge stored in the thin insulation film 12.
The present inventor's experiment shows that the minimum intensity of electric field to generate electron trap sites in the film 12 ranges between 4.5 and 5 MV/cm. However, such a low electric field does not substantially give rise to the flow of tunnel current, thereby failing to cause electric charge to be introduced into or drawn out from the floating gate.